#ifndef _ISHARKL2_DFS_H

#define _ISHARKL2_DFS_H

#include "isharkl2_base_common.h"

#define DEBUG_DFS_TEST

#define DFS_FREQ_NUM 	4

#define	PUB0_SOFT_DFS_CTRL		(PUB0_APB_RF_PUB0_BASE+0x8000)
#define	PUB0_HARD_DFS_CTRL_LO	(PUB0_APB_RF_PUB0_BASE+0x8004)
#define	PUB0_HARD_DFS_CTRL_HI	(PUB0_APB_RF_PUB0_BASE+0x8008)
#define	PUB0_BIST_TEST_CTRL		(PUB0_APB_RF_PUB0_BASE+0x8028)
#define	PUB0_LP_GEN_CTRL			(PUB0_APB_RF_PUB0_BASE+0x802c)
#define	PUB0_PURE_SW_DFS_CTRL	(PUB0_APB_RF_PUB0_BASE+0x8030)


#define AON_APB_CGM_CFG					(AON_APB_CTL_BASE +0X0098)
#define AON_APB_CGM_CLK_TOP_REG1		(AON_APB_CTL_BASE +0X013c)
#define AON_APB_PUB_CTRL					(AON_APB_CTL_BASE +0x01e4)
#define AON_APB_PUB_FC_CTRL				(AON_APB_CTL_BASE +0X01e0)
#define PUB_FC_CTRL 						(AON_APB_CTL_BASE +0x01E0)
#define AON_RC100M_CFG						(AON_APB_CTL_BASE +0x0134)



enum DFS_REQ_SRC
{
	DFI_BM_REQ=0,
	AXI_BM_REQ=1,
	SW_MAILBOX_REQ=2
};

enum BM_INT_STATUS_E
{
	UP_FREQ_NO_INT=0,
	DOWN_FREQ_NO_INT=1,
	UP_FREQ=2,
	DOWN_FREQ=3
};

enum DFS_STATUS_E
{
	DFS_UP=0,
	DFS_DOWN=1
};

enum DFS_SOFT_MODE
{
	CHANGE_FREQ=0,
	CHANGE_DIS=1,
	CHANGE_LOWEST=2,
	CHANGE_HIGHEST=3
};


extern void ddr_dfs_reg_cfg();
extern void dfs_test();
#endif


